SOC的可测性设计策略

DFT Strategy of SOC

通过一则设计实例研究SOC(System On Chip)的可测性设计策略;15针对系统中的特殊模块采取专用的可测性策略,如对存储器进行内建自测试,对锁相环测试其性能参数等;其它模块采用基于ATPG(Automatic Test Pattern Generation)的结构化测试方法进行测试,同时设计一些控制模块优化测试结构;经验证,应用这些策略,在满足了功耗和面积要求的前提下,系统总测试覆盖率达到了98.69%,且具有期望的可控制性和可观察性;因此在SOC设计中应灵活采用不同测试策略,合理分配测试资源从而达到预期的测试效果。

Through the studies of a real case involving DFT （Design For Test） strategy of SOC （System On Chip）, targeting on special modules , appropriate DFT strategies are adopted such as memory testing using MBIST （Memory Built--In Self Test）, special function verification of the PLL （Phase Locked Loop） and so on, and testing the rest modules with ATPG （Automatic Test Pattern Generation）. In addition, various modules are designed to optimize the testing circuitry. It has been proven that through the testing strategies listed above, power consumption and area were met the specification, and the test coverage is optimized by 98. 69%, which makes the testable circuitry both controllable and observable. Therefore in SOC design the DFT strategies and resources should be assigned efficiently in order to get the expected testing results.