摘要
A low jitter All-Digital Phase-Locked Loop(ADPLL) used as a clock generator is designed.The Digital-Controlled Oscillator(DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable.Based on the Impulse Sensitivity Function(ISF) analysis,an effective way is proposed to reduce the ADPLL's jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one.The ADPLL is implemented in a 0.18μm CMOS process with 1.8V supply voltage,occupies 0.046mm2 of on-chip area.According to the measured results,the ADPLL can operate from 108MHz to 304MHz,and the peak-to-peak jitter is 139ps when the DCO's output frequency is 188MHz.
A low jitter All-Digital Phase-Locked Loop (ADPLL) used as a clock generator is designed. The Digital-Controlled Oscillator (DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function (ISF) analysis, an effective way is proposed to reduce the ADPLL's jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO's output frequency is 188MHz.
关键词
全数字锁相环
数字控制振荡器
脉冲灵敏度函数
热噪声
速度偏差
All-Digital Phase Locked Loop (ADPLL)
Digital Controlled Oscillator (DCO)
Impulse Sensitivity Function (ISF)
Thermal noise
Jitter