摘要
Information appliance is the combination of traditional home appliances and the internet technology. In this article, an Ethernet controller system-on-chip （SOC） solution for information appliances is presented. To achieve high performance, the embedded 8 bits 8051 micro control unit （MCU） is optimized by an independent instruction bus and a data bus. Besides, a two-stage pipeline feature is added. Compared with the existing 8051 core, the enhanced one-cycle MCU offers ten times improvement in instruction execution efficiency. Meanwhile, the performance of media access control （MAC） circuit is greatly improved by adopting various techniques such as direct memory access （DMA） control, paging strategy, etc. To reduce the power consumption, clock gating, low power supply, and multi-working-clock are adopted. Moreover, to achieve rapid data communication in different clock frequency circuits, a simple ping-pong first in first out （FIFO） circuit is realized. The chip is implemented using TSMC 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology. Its die area is 4.8 min× 4.6 mm. The test results show that the maximum throughput of Ethernet packets can reach 7 Mb/s while the power consumption is rather low-the working current is just about 200 mA.
Information appliance is the combination of traditional home appliances and the internet technology. In this article, an Ethernet controller system-on-chip （SOC） solution for information appliances is presented. To achieve high performance, the embedded 8 bits 8051 micro control unit （MCU） is optimized by an independent instruction bus and a data bus. Besides, a two-stage pipeline feature is added. Compared with the existing 8051 core, the enhanced one-cycle MCU offers ten times improvement in instruction execution efficiency. Meanwhile, the performance of media access control （MAC） circuit is greatly improved by adopting various techniques such as direct memory access （DMA） control, paging strategy, etc. To reduce the power consumption, clock gating, low power supply, and multi-working-clock are adopted. Moreover, to achieve rapid data communication in different clock frequency circuits, a simple ping-pong first in first out （FIFO） circuit is realized. The chip is implemented using TSMC 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology. Its die area is 4.8 min× 4.6 mm. The test results show that the maximum throughput of Ethernet packets can reach 7 Mb/s while the power consumption is rather low-the working current is just about 200 mA.
基金
the Hi-Tech Research and Development Program of China (2006AA01Z226)
