适用于流水线ADC采样保持电路的设计

The design of a Sample/ Hold Circuit for Pipelined A/D Converter

文章介绍了一种适用于10位40MS/s流水线A/D转换器的采样/保持(S/H)电路。整个电路的设计基于TSMC的0.25um工艺,在电源电压为2.5V的情况下,采样信号全差分幅度为1V。通过采用全差分flip-around结构,而非传统的电荷传输构架,因而在同等精度下,大大降低了功耗。为了达到高精度,高采样速率的要求,该S/H电路采用高增益,宽带宽的的两级运算放大器。

A low power sample-and-hold circuit for a 10-bit 40 MS/ s pipelined A/D converter has been designed ,Simulated with 0. 25μxm CMOS process and 2. 5 V supply power , the full scale of the sampled fully differential signal is 1 V. Instead of the traditional charge transfer architecture , a fully difierential flip-around architecture is used to reduce the power consumption. In order to achieve the requirement of high resolution and quickly sample ,a high gain and expanse bandwidth two-stage opa is used.