低功耗三输入异或(XOR)门
摘要
基于常用三输入异或(XOR)门实现方法的分析,设计了一种新的基于晶体管级的三输入XOR门电路.与已公开发表的典型电路相比较,文中所建议的电路具有低功耗和低功耗延迟积(PDP)的特性.
基金
国家自然科学基金(批准号:60676017)
浙江省自然科学基金人才专项(批准号:R105614)
浙江省科技厅科技计划(批准号:2007C24017)
教育部留学回国基金资助项目
参考文献11
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1Bui H, Wang Y, Jiang Y. Design and analysis of low-power 10- transistor full adders using novel XOR-XNOR gates. IEEE Transactions on Circuits and Systems Ⅱ: Analog and Digital Signal Processing, 2002, 49(1): 25-30
-
2Suzuki M, Ohkubo N, Shinbo T, et al. A 1.5ns 32-b CMOS ALU in double pass-transistor logic. IEEE Journal of Solid-state Circuits, 1993, 28(11): 1145-1151
-
3Ahmed MS, Magdy AB. A novel high-performance CMOS 1 bit full-adder cell. IEEE Transactions on Circuits and Systems-Ⅱ: Analog and Digital Signal Processing, 2000, 47(5): 478-481
-
4卢君明,徐锋,胡鹏飞.低电压低功耗全加器的研究设计[J].固体电子学研究与进展,2004,24(3):369-372. 被引量：6
-
5Zhuang N, Wu H. A new design of the CMOS full adder. IEEE Journal of Solid State Circuits, 1992, 27(5) : 840-844
-
6Wang JM, Fang SC, Feng WS. New efficient designs for XOR and XNOR functions on the transistor level. IEEE Journal of Solid-State Circuits, 1994, 29(7): 780-786
-
7Lee H, Sobelman GE. New XOR/XNOR and full adder circuits for low voltage, low power applications. Microelectronics Journal, 1998, 29:509-517
-
8Sumeer G, Mohamed AE, Magdy AB. Novel design methodology for high performance XOR-XNOR circuit design. Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI' 03), 2003
-
9Fang SC, Wang JM, Feng WS. A new direct design for three-input XOR function on the transistor level. IEEE Transactions on Circuits and Systems-Ⅰ: Fund A mental Theory and Applications, 1996, 43(4): 343-348
-
10Cheng KH, Hsieh VC. High efficient 3-input XOR for low-voltage low-power high-speed applications. Proceedings of Asia Pa cific Conference on Advance System Integrated Circuits (APASIC' 99), 1999
二级参考文献8
-
1[1]Weste N,Eshraghian K.Principles of CMOS VLSI Design,a System Perspective,Reading,MA:Addiso-Wesley,1993
-
2[2]Zhuang N,Wu H.A new design of the CMOS full adder.IEEE J Solid-State Circuits,1992;27(5):840～844
-
3[3]Abu-Shama E,bayoumi M.A new cell for low power adders.Proc Int Midwest Symp Circuits and Systems,1995;1 014～1 017
-
4[4]Shams A,Bayoumi M.A modular approach for designing low power adders.Proc ASILOMAR,1997:757～761
-
5[5]Shams A M,Bayoumi M A.A novel high-performance CMOS 1-bit full-adder cell.IEEE J Solid-State Circuit and Systems-Ⅱ,2000;47(5):478～481
-
6[6]Wang J M,Fang S C,Feng W S.New efficient designs for XOR and XNOR functions on the transistor level.IEEE J Solid-State Circuit,1994;29(7):780～786
-
7[7]Lee H,Sobelman G E.New XOR/XNOR and full adder circuits for low voltage,low power applications.Microelectronics Journal,1998;29:509～517
-
8[8]Shams A,Bayoumi M.Performance evaluation of 1-bit CMOS adder cells.Proc IEEE Int Symp Circuits and Systems,ISCAS'99,1999;1:27～30
共引文献5
-
1张爱华,夏银水.低功耗全加器的电路设计[J].浙江大学学报（理学版）,2008,35(5):534-537. 被引量：4
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2方赟,蔡艳慧,钟传杰.一种基于多数决定门的新型全加器的设计[J].微电子学,2010,40(4):561-565. 被引量：1
-
3刘政林,郭超,霍文捷.基于SHA-1引擎的嵌入式安全协处理器设计[J].华中科技大学学报（自然科学版）,2011,39(8):72-75. 被引量：1
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4周大鹏,张自友,何光普.基于多数决定逻辑的一位全加器设计[J].科技通报,2012,28(6):155-157.
-
5欧阳励行.任意长度加法器的设计与分析[J].中国高新科技,2018(21):74-75.
