CAN总线中CRC编码的硬件实现

Hardware Implementation of CRC Encoding in CAN bus

基于CAN总线数据传输过程中加入的CRC编码技术与原理,本文首先给出了比特串行CRC编码原理及基于除法编码运算的CRC编码算法硬件实现方法。然而,为了满足高速数据传输的需要,本文进一步给出了,利用空间换取时间的比特并行CRC编码算法的详细推导过程,最后是采用VHDL语言与FPGA器件,完成了CAN总线中比特并行CRC编码算法的硬件仿真、综合、布线及下载配置,结果表明完全达到了预期的设计要求。

In the article, the CRC principle is introduced at first. The particular deduction of bit parallel CRC algorithm is shown. At the end of article, the hardware implementation of bit parallel CRC algorithm in CAN bus is described with VHDL language and FPGA. The result indicates the anticipate design request is accomplished.