简易逻辑分析仪设计

Design of simple logic analyzer

本系统是以STC89C52单片机和复杂可编程逻辑器件CPLD的组合电路为核心,利用锁存器在时钟上升沿将输入端的数据锁存的原理,构建了一个基于实时采样和直接数据存储器存储(DMA)的简易逻辑分析仪。系统由五部分组成:按键模块、CPLD模块、DDS采样时钟发生模块、LCD显示模块、DMA数据采集模块。相比于市场上的逻辑分析仪,本系统结构简单,易制作,成本低,可同时测量8路TTL信号。本系统可以用来分析数字逻辑电路中的时序逻辑关系,本文还用该逻辑分析仪研究了51单片机对外部地址读写操作的时序,得到与单片机数据手册一致的波形时序图。

A simple logic analyzer based on a real-time sampling and DMA has been designed by using STC89C52 SCM and CPLD circuit as the primary components. It operates by a latch which can latch the data coming from the input port on the output port by means of latching the rising edge of a clock pulse. The system includes five basic components： a button control module, the CPLD module, a DDS sampling clock pulse generation module, an LCD module, and the DMA module. Compared to the existing logic analyzer, the system can measure synchronously 8 TTL signals, and the circuit is simple and can be constructed easily with low costs. The system can be used as a tool that measures the logic relations of the digital circuit. An example has been given that shows how the time is measured when a 51 SCM reads or writes some data to the outside address, SCM manual data are consistent with the wave timing map.