时空混沌伪随机比特发生器及其FPGA实现

Pseudo-random bit generator based on spatio-temporal chaos and its FPGA implementation

利用时空混沌双向耦合映象格子模型构建了一种伪随机比特发生器,并在FPGA芯片上实现。通过分析系统的最大Lyapunov指数得到系统参数的选择标准。在不考虑通信时延的情况下,该伪随机比特发生器的比特产生速度可达到512 Mbps。使用美国国家标准和技术局(NIST)的FIPS 140-2及SP 800-22测试标准对该伪随机比特发生器实际输出的伪随机比特序列进行了测试,实验结果表明该发生器所产生的伪随机比特序列随机性能良好。

A pseudo-random bit generator （PRBG） based on a spatio-temporal chaotic bi-directional coupled map lattice model is designed and implemented on an FPGA chip. The parameter selection criterion of the generator is established in terms of the largest Lyapunov exponent. Without taking the communication delay into account, the implemented PRBG chip achieves a throughput of 512 Mbps. Both FIPS 140-2 and SP 800-22 testing suites issued by the National Institute of Standards and Technology of the United States are employed to evaluate the performance of the generated pseudo-random bit sequence, showing satisfactory results.