虚拟FPGA逻辑验证分析仪的设计

The Design of Virtual FPGA Logic Verification Analyzer

本文对一种虚拟FPGA逻辑验证分析仪的设计方案及其工作原理进行了研究，并详细介绍了该仪器的两个主要工作环节的设计。采用FPGA技术来实现仪器硬件部分的主要设计，应用图形化编程语言LabVIEW来实现仪器的软件设计。在该仪器研制中，创新性地将逻辑分析仪和激励信号配合使用，实现了FPGA中电路的基本测试验证功能。同时，它还具有逻辑分析仪和产生激励信号的功能。

The design scheme and the basic principle of a Virtual FPGA Logic Verification Analyzer are studied in this paper. And the design of two main work processes of the verification analyzer is introduced in detail. The major design of the hardware part of this instrument is realized by using FPGA technology, while the software design is realized through Lab View Professional In the design, the logic analyzer and the excitation signal are innovatively cooperated, thus leading to the implementation of the basic testing and validation functions of the circuits in the FPGA. At the same time, the functions of logic analyzer and the excitation signal source are also realized.