二维9/7整数离散小波变换的FPGA设计

FPGA design of 2-D 9/7 integer discrete wavelet transform

采用流水线设计技术和模块化设计思想,提出一种基于CCSDS新推荐标准的图像数据压缩算法中二维9/7整数离散小波变换的实时并行实现结构。结构主要由行变换、列变换和行缓存等模块组成,行、列变换可并行进行。使用FPGA内嵌的BlockRAM作为行缓存器,减少了外部存储器的使用、访问以及时间延迟。结果表明,该实现结构能够减少运算量和电路规模,获得较高的吞吐率,增加硬件资源利用率,提高变换速度。

A real-time and parallel implementation architecture that performed a 2-D 9/7 integer discrete wavelet transform for image data compression of the new CCSDS recommendation standard is proposed using the pipeline and the module design. The architecture mainly consists of one row transform module, one column transform module and row buffers module, etc. The whole architecture is optimized to make the row transform and column transform operate in parallel. The utilization of Block- RAM in FPGA can reduce the amotmt of external memory and the latency. The result shows that the implementation can reduce the computation, get higher throughput, achieve higher hardware utilization and speed up the transformation.