一种基于VHDL的乒乓操作控制法的研究

Research on pipeline control method based on VHDL

本文将乒乓操作的控制方法应用于双通道频率/数字的数据采集中,介绍了这种逻辑结构的设计。重点论述了在VHDL中,如何通过脉冲信号边沿(上升沿或下降沿)的脉冲化,信号延迟分析和初始值保持等方法来实现这种由双沿信号产生的逻辑控制信号的方法。这样就解决了在VHDL一个PROCESS过程语句中不能实现双沿判断的缺点。这种控制方法延时小,整个过程的动作衔接紧密,自动化程度较高。同时,可以通过提高采集时钟CLK的频率来进一步减小延时。本方法在QUARTERSⅱ5.1软件中通过时序仿真,并下载到cycloneⅱ芯片中验证,完全能满足设计的要求。

This paper discusses a kind of method that how to applies the pipeline technodogy to data acquisition in double channel Frequency/Data conversion. The design of this logic structure is described. Moreover, emphases are put on the details that how the signal for control is generated by means of converting either edge of the pulse into a pulse, analyzing the delay of the signal and holding the original value. So, the defect that the double edge can＇t be sprung together in a PROCESS in VHDL could be solved, and the delay of this control method can be limited to a very small value. With this kind of logic control, the behavior goes smoothly without stop. This design has been successfully simulated in QUARTERS ii 5.1 and tested in cyclone ii chip.