高性能多模可编程CMOS输出缓冲器的研究实现

High Performance Multi-Modulus Programmable CMOS Output Buffer

提出了一种应用于专用集成电路(ASIC)和FPGA高速IO接口的通用型数据输出缓冲器(Output Buffer)及其ESD(Electrostatic Discharge)保护电路。电路采用新型三组电源供电模式,通过编程点精确控制输出驱动能力,支持多达16种最常用的数据传输协议,电路采用SMIC0.18μm CMOS MM工艺实现。仿真结果表明:output buffer输出信号可满足所有协议的电气要求,支持的所有协议均至少可在250MHz频率下进行数据传输,传输延迟保持在660ps^1180ps之间。

A general purpose output Buffer with ESD for IO blocks of ASIC and FPGA is proposed in this paper. The output buffer is supplied by three power sources, and its driving ability can be exactly controlled by the digital signal so that it supports 16 selectable IO standards. The output Buffer and its ESD are implemented with SMIC 0. 18 ban MM CMOS technology. The simulation results show that the output Buffer could be worked at 250 MHz for all IO standards and the transport lag is between 660 ps and 1180 ps.