摘要
本文提出一种沟道长度为0.125μm的异质结CMOS(HCMOS)器件结构。在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析。模拟结果表明,相对于体SiCMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成。
An integration of 0. 125 μm dual-strained SiGe/Si heterojunction CMOSFET (HCMOSFET) structure is presented in this paper. Compressive strained SiGe and tensile strained Si are used as channel material for heterojunction PMOSFET (HPMOS) and heterojunction NMOSFET (HNMOS) respectively, HPMOS and HNMOS are vertically stacked in this structure; the parameters of mobility models of electrons and holes in strained SiGe and strained Si are modified for exact simulation; DC and AC electrical characteristics of this device and its input-output characteristics are finally simulated and analyzed by simu- lator Medici. The simulation results indicate that this device exhibits significant enhancements in these electrical characteristics, correct logic function and shorter delay time than bulk Si CMOS. Simultaneously, almost 50% layout area in packing density can be saved in comparison with that of bulk Si CMOS.
出处
《电子器件》
CAS
2008年第5期1495-1500,共6页
Chinese Journal of Electron Devices
基金
武器装备预研基金项目(51408061104DZ01)