基于并行机制的边界扫描技术

Boundary Scan Technique Based on the Parallel Test Access Mechanism

在SoC测试时,测试功耗和测试成本是其可测性设计中最重要的一点要求。在分析了常见测试结构的测试功耗的基础上,提出了一种并行扫描机制的测试结构,包括访问机制的设计和测试控制器的设计。该方法可根据测试成本和测试功耗的要求,选择不同的构造方法。

The test power dissipation is one of the critical facts which should be considered carefully when designing the SoC for testability, so a parallel boundary scan TAM and its test controller are proposed. The TAM and the controller can be selected flexible for the test cost and the power dissipation.