一种开关移位式32位乘法器的设计

A 32 bit Multiplier Design Based on Switch & Shift

乘法器在CPU的ALU设计中是很重要,也是较为复杂的一部分,它占据大的面积和较长的延时。根据系统不同的要求,我们可以设计出不同的乘法器。本文是在系统时钟要求和面积两方的限制下做了折衷,提出了一种基于开关和移位工作方式的多时钟周期乘法器的设计。最后用DC进行综合,并经VCS仿真得到结果与SYNOPSYS公司design_ware里的乘法器进行比较,指出其优缺点。

The multiplier is an important and complex part in the ALU design ot CPU, it takes up a relative larger area and longer delay. According to the different requirements of system, we can design out various multipliers. This paper makes a compromise between system clock and area, bringing out a none single clock multiplier design based on switch and shift operation. At last by using SYNOPSYS tools it gives out the synthesis report and simulating wave to draw a parallel between this multiplier and the one generated from SYNOPSYS designware.