基于MBIST的多片SRAM联合测试实现

Implementing of Multi-SRAM Co-Test Based on MBIST

现代ASIC设计中,存储器特别是SRAM的使用必不可少,用于存放大量数据。在稍微大的电路设计中,可能会需要多片不同大小的SRAM以配合整体工作。用EDA软件当然能够生成对应的MBIST电路代码,但多片SRAM会产生多个这样的控制电路,这无疑产生了不必要的浪费。从自身设计的单片SRAM的MBIST电路出发,基于此提出只用一个MBIST控制电路实现多片不同大小SRAM联合测试的方案,并给出综合报告以及其仿真结果。

In the modern ASIC design,the using of SRAM is necessary for storing data. Especially in some larger designs, multi-SRAM with different sizes are needed to assist the entire work. Of course by using EDA software, we can generate the MBIST circuit in the format of verilog code, but it introduces the unnecessary waste of resources since we need multiple such kind of circuit. This paper brings forward a scheme that by only one MBIST control circuit we can carry out the tests of multi-SRAM with various sizes. At last it gives out the synthesis reports and simulation results.