基于硬件优化的H.264 VBSME SAD算法及其VLSI结构

A H.264 VBSME SAD Algorithm and Architecture for Hardware Optimization

以硬件代价优化为目的,对H.264宏块级的VBSME SAD VLSI结构进行了详细的分析,提出一种像素平滑重采样的SAD算法及其VLSI结构.该算法先将当前块和参考块像素划分成2×2的子块进行平滑和重采样,再进行7种可变块大小的SAD运算,以有效地降低SAD运算中级联加法器的深度和宽度,减少硬件代价.实验结果表明,该算法的编码性能与SAD标准算法的RDO曲线相比偏差小于1%,而硬件面积和功耗在不同的综合时钟频率下可节省53%以上.鉴于其优良的硬件性能,文中算法及其结构非常适合高并行度的H.264 VLSI解决方案.

The hardware performance of H. 264 macroblock-parallel VBSME SAD structure is discussed, and a novel pixel smoothing and resampling algorithm is proposed for hardware optimization. In this SAD algorithm, the current and reference pixels are partitioned into 2 X 2 subblocks, then smoothed and resampled for seven variable-block-size SAD calculations. It can effectively decrease the depth and width of cascaded adder for hardware reduction. Experimental results show that the proposed algorithm and its architecture can save over 53% hardware and power cost but only causes less than 1% RDO loss. It is very suitable for high-parallelism H. 264 VLSI solutions due to its excellent hardware performance.