期刊文献+

应用于泛在计算的认证电路

Authentication circuit used in ubiquitous computing
下载PDF
导出
摘要 分别采用高级加密标准(AES)、无线局域网认证和保密基础密码算法(SMS4)以及散列函数(SHA-1)实现了用于泛在计算的认证电路.在考虑吞吐率条件下,定义能耗变量来衡量不同的电路实现对功耗的优化效果,在此基础上分析了AES中不同结构S盒的影响以及SHA中改进迭代的方法.上述电路采用0.25μm1.8V CMOS工艺实现,比较了不同认证电路的面积、吞吐率和能耗特性,结果表明:对AES电路进行简单的优化即可使其具有低能耗、高吞吐率的特性,因此更合适作为泛在计算中的认证电路. Several of circuit implementations of authentication for ubiquitous computing were presented, using advanced encryption standard (AES), wireless local area network authentication and privacy infrastructure encryption algorithm (SMS4), and security Hash algorithm (SHA-1). Considering the throughput of different implementations, an energy consumption parameter is derived to evaluate the low-power design strategy. Different S-boxes comparison in AES and round calculation improvement are proposed to optimize throughput and energy consumption. These circuits were implemented with 0.25 μm 1.8 V CMOS (complementary metal-oxide-semiconductor) standard cell library, and comparisons were performed in area, throughput and energy for different authentication implementations. The results demonstrate that AES is a preferable choice for its potential of high throughput and low energy dissipation at very low hardware cost.
出处 《华中科技大学学报(自然科学版)》 EI CAS CSCD 北大核心 2008年第9期33-36,共4页 Journal of Huazhong University of Science and Technology(Natural Science Edition)
基金 国家高技术研究发展计划资助项目(2006AA01Z226) 湖北省自然科学基金资助项目(2006ABA080) 新世纪优秀人才支持计划资助项目(NCET-07-0328) 华中科技大学基金重点资助项目(2006Z011B)
关键词 加密算法 泛在计算 认证电路 高级加密标准 安全散列算法 encryption algorithm ubiquitous computing authentication circuit advanced encryptionstandard security Hash algorithm
  • 相关文献

参考文献8

  • 1Choi Yongje, Kim Mooseop, Kim Taesung, et al. Low power implementation of SHA 1 algorithm for RFID system [C] // Proceeding of ISCE 2006. New York: IEEE Press, 2006: 1-5.
  • 2Sastry N, Wagner D. Security considerations for IEEE 802. 15. 4 networks [C] // Proceeding of the 2004 ACM Workshop on Wireless Security. New York: ACM Press, 2004: 32-42.
  • 3Etbaz R, Champagne D, Lee R B, et al. TEC-tree: a low-cost, parallelizable tree for efficient defense against memory replay attacks [C] // Proceeding of CHES 2007. Berlin: Springer-Verlag, 2007: 289- 302.
  • 4Bertoni G, Macchetti M, Negri L, et al. Power-efficient ASIC synthesis of cryptographic Sboxes[C]// Proceeding of GLSVLSI. New York: ACM Press, 2005: 277-281.
  • 5XING Ji-peng ZOU Xue-cheng GUO Xu.Ultra-low power S-Boxes architecture for AES[J].The Journal of China Universities of Posts and Telecommunications,2008,15(1):112-117. 被引量:2
  • 6Wolkerstorfer J, Oswald E, Lamberger M. An ASIC implementation of the AES S-boxes[C] // Proceeding of Asiacrypt 2001. Berlin: Springer-Verlag, 2001: 239-254.
  • 7Morioka S, Satoh A. An optimized S-box circuit architecture for low power AES design[C]//Proceeding of CHES 2002. Berlin: Springer-Verlag, 2002: 172-186.
  • 8陈毅成,邹雪城,刘政林,刘菊.用于无线传感器网络的AES协处理器设计[J].华中科技大学学报(自然科学版),2007,35(8):30-32. 被引量:4

二级参考文献19

  • 1柯于辉,李红艳,李承军.基于互联网的过程控制系统的安全性设计[J].华中科技大学学报(自然科学版),2004,32(9):31-33. 被引量:6
  • 2AES. Federal Information Processing Standards Publication 197, 2001
  • 3Hodjat A, Verbauwhede I. A 21.54 Gb/s fully pipelined AES processor on FPGA. Proceedings of 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04). Apt 20-23, 2004 Napa, CA, USA. Los Alamitos, CA, USA: IEEE Computer Society, 2004:308-309
  • 4Fischer V, Drutarovsky M. Two methods of Rijndael implementation in reconfiguration hardware. Proceedings of 3rd International Workshop on Cryptographic Hardware and Embedded Systems (CHES'01). May 14-16, 2001, Paris, France. Heidelberg, Germany: Springer verlag, 2001:77-92
  • 5Elbirt A J, Yip W, Chetwynd B, et al. An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2001, 9(4): 545-557
  • 6Verbauwhede I, Schaumont P, Kuo H. Design and performance testing of a 2.29-GB/s Rijndael processor. IEEE Journal of Solid-State Circuits, 2003, 38(3): 569-572
  • 7Morioka S, Satoh A. A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(7): 686--691
  • 8Wolkerstorfer J, Oswald E, Lamberger M. An ASIC Implementation of the AES S-Boxes. Proceedings of Cryptographer's Track at the RSA Conference, Feb 18-22, 2002, San Jose, CA, USA Heidelberg, Germany: Springer verlag, 2002:67-78
  • 9Morioka S, Satoh A. An optimized S-boxes circuit architecture for low power AES design. Proceedings of 4th International Workshop on Cryptographic Hardware and Einbedded Systems (CHES'02), Aug 13-15, 2002, San Francisco: CA, USA, Heidelberg, Germany: Springer verlag, 2002:172-186
  • 10Bryant R E. Graph-based algorithms for Boolean function manipulation. IEEE Transactions on Computer, 1986, 35(8): 677-691

共引文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部