新型高电源抑制比CMOS电流基准

Novel CMOS current reference with high power-supply rejection ratio

为提高CMOS集成电路中电流基准的精度和稳定性，提出了一种结构简单，电源抑制比（PSRR）很高的电流基准结构——三支路电流基准．应用基尔霍夫定律（Kirchhoff’s current and voltage law，Kcl Kvl）和偏微分方程，对比分析了传统的电流基准、共源共栅电流基准以及三支路电流基准的小信号模型，求解出了这3种电路的电源抑制比公式．对比发现传统电流基准和共源共栅电流基准的节点电压正反馈限制了电流基准的性能，三支路结构由于节点电压成强负反馈，拥有更高的PSRR．三支路电流基准采用了一阶温度补偿方案，保证了温度稳定性．经CSMC0．5μm工艺仿真结果显示，三支路基准在输入电压1．5～5．0V的低频PSRR达-77．9dB，明显优于另外两种结构；在～20～120℃温度区间内输出电流稳定性达到了255×10^-6／℃，满足了大多数应用的要求．

A simple triple-branch current reference with high power-supply rejection ratio （PSRR） was proposed to enhance the accuracy and stability of current reference of CMOS integrated circuits. Using Kirch- hoff＇s current and voltage law （Kvl, Kcl） and partial differential equations, the small-signal models of conventional and cascade current references were compared with that of the triple-branch current reference, and the PSRRS of these three circuits are solved. The results showed that the PSRR performances of conventional and cascade current references were confined due to the positive feedback loop of node voltage in them, while the triple-branch current reference has a much higher PSRR due to the strong negative feedback loop of node voltage. First order temperature compensation is also adopted in the triple-branch current reference to provide temperature stability. Using CSMC 0.5 μm process, simulation showed that when the input voltage was 1.5-5.0 V, the triple-branch current reference＇s PSRR reached -77.9 dB, apparently better than those of conventional and cascade current references; and temperature drift within range of -20-120 ℃ was below 255×10^-6/℃, which is adequate for most applications.