一种改进的插值定时恢复结构

A Modified Interpolation for Timing Recovery in Digital Synchronous Systems

在数字同步接收系统中使用插值法提取定时信号的过程中,由于插值滤波器的频域特性是非理想的,为了减小插值器频域内的失真而引起的插值误差,提出了一种改进型的插值结构。该方法在插值之前对输入的信号进行上采样,分析表明该方法可降低插值滤波器的阶数,减少乘法器的使用,从而大大地减少了运算量,降低了系统的实现成本。

In the process of capturing the timing component by using the method of interpolation in a digital synchronous system, an improved interpolation configuration is proposed for reducing the interpolation error resulting from the distortion in the frequency domain of the interpolator, since the spectral characteristics of the interpolation filter is not ideal. The up-sampling of input signals is done before interpolating. By analyzing thoroughly this method it can be shown that the order of the interpolation filter is lowered, the utilization of multiplier is much less and the operation as well as the cost of the system is greatly reduced. Simulation results show that the method is of effective improvement on the system performance.