3阶锁相环路接收机的设计与实现

Design and implementation of third-order PLL receivers

低阶锁相环跟踪频率斜升信号时产生的稳态相差致使环路失锁,接收机无法锁定载波信号.针对这一问题提出一种具有3个零极点的3阶锁相环路,其产生零稳态相差,对含有多普勒频移的载波信号具有较好的锁定效果.给出3阶锁相环参数设计公式.使用频率预测预置锁相环中心频率使环路快速捕获信号,利用FFT及卡尔曼滤波方法提高频率预测的精度,采用FPGA实现3阶载波接收机.结果显示,3阶PLL可稳定跟踪载波信号.

Due to steady phase error, low-order PLL has a trouble in tracking frequency ramp signals, so that the receiver cannot lock carrier signals. This paper proposed a type of third-order PLL with three zero poles, hence it had better locking effect on carrier signals with Doppler shift since it generated zero phase errors. The design expressions for third-order PLL＇s parameters were given. With this method, the central frequency of PLL was used to quickly capture signals. The FFT and Kalman filtering were employed to improve the precision of frequency prediction; and the FPGA was utilized to implement a third-order carrier receiver. The research outcome showed that the proposed third-order carrier receiver can track carrier signals steadily.