摘要
文中采用双环系统,基于改进的Hogge鉴相器,差分电荷泵,以及一个四级环形压控振荡器实现了一种全集成的CMOS时钟恢复电路,时钟恢复的频率为125MHz,该电路最大程度上的减小了电荷注入、电荷分享等寄生效应的影响。增加一个偏置电路使各模块的工作电源电压降低到2.94V,整个芯片的功耗降低10%。
A fully integrated CMOS clock recovery circuit is implemented by adopting a double ring system, an improved Hogge phase detector, a difference charge pump and a four stage ring voltage control oscillator. The frequency of the recovered clock is 125 MHz. This circuit greatly reduces the autoeciousness effects of charge injection, charge sharing and etc. By using a bias circuit, the working power voltage of every block is reduced to 2. 9 V, and the power consumption of the whole chip is decreased by 10%.
出处
《电子科技》
2008年第10期19-23,共5页
Electronic Science and Technology
关键词
以太网
时钟恢复
低功耗
ethernet
clock recovery
low power
