自适应码率QC-LDPC码编码器的FPGA实现

FPGA implementation of adaptive code rate QC-LDPC encoder

准循环低密度奇偶校验码(QC-LDPC codes)相比其他的LDPC码具有简单的编码结构,拥有较好的应用前景。通过构造校验矩阵设计了不同码率和不同帧长的具有系统结构的QC-LDPC码,并分析了这些码的性能,随后将编码过程分阶段引入主从控制模块及复用基本SRAA组,设计了变码率和变帧长的编码器,并用Verilog HDL语言在Spartan 3 3s1500fg676芯片上实现了编码器的设计。综合报告表明:在使用适中的硬件资源情况下,系统最大频率达到了174.856 MHz,能满足高速编码的要求。

Quasi-cyclic （QC） low-density parity-check （LDPC） codes have encoding advantage over other types of LDPC codes for their simple coding structure. Different rates and frames QC-LDPC codes in systematic-circulant （SC） form were designed by constructing the parity check matrix, and their performance was analyzed. The design introduced two controlmodules and reused SRAA circuits to realize multi-rate encoding. The encoder was implemented with Verilog HDL language on the chip of Spartan 3 3s1500fg676. Synthesis report shows that the system＇s max frequency is 174.856 MHz with mezzo hardware device and satisfies the demand of high rate-encoding application.