摘要
A sub-mA phase-locked loop fabricated in a 65nm standard digital CMOS process is presented. The impact of process variation is largely removed by a novel open-loop calibration that is performed only during start-up but is opened during normal operation. This method reduces calibration time significantly compared with its closed-loop counterpart. The dual-loop PLL architecture is adopted to achieve a process-independent damping factor and pole-zero separation. A new phase frequency detector embedded with a level shifter is introduced. Careful power partitioning is explored to minimize the noise coupling. The proposed PLL achieves 3. lps RMS jitter running at 1.6GHz while consuming only 0.94mA.
介绍了一个用于高速信号传输的低功耗锁相环.提出了一种新的开环校准方法.该校准通过上电时候进行的开环数字校准很大程度上减轻了工艺变化对电路的影响,相比以前的闭环校准方法,该方法可以显著缩短校准时间.在这个锁相环中采用了双环路的结构来获得对工艺、温度和环境变化不敏感的环路参数:例如衰减因子、相位裕度等.还设计了一种新的鉴频鉴相器,它内嵌了电平转换的功能,简化了电路.该PLL的设计通过小心的供电网络划分来降低电源噪声的耦合.设计的锁相环路在输出为1.6GHz的时候均方根抖动为3.1ps,而仅消耗约为1mA的电流.
基金
国家自然科学基金(批准号:60673146,60703017,60736012)
国家高技术研究发展计划(批准号:2007AA01Z114)
国家重点基础研究发展计划(批准号:2005CB321600)资助项目~~
