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MOS Model 20 Based RF-SOI LDMOS Large-Signal Modeling

基于MOS Model 20的RF-SOI LDMOS大信号建模(英文)
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摘要 A novel large-signal equivalent circuit model of RF-SOI LDMOS based on Philips MOS Model 20 (MM20) is presented. The weak avalanche effect and the power dissipation caused by self-heating are described. The RF parasitic elements are extracted directly from measured S-parameters with analytical methods. Their final values can be obtained quickly and accurately through the necessary optimization. The model is validated in DC,AC small-signal,and large-signal analyses for an RF-SOI LDMOS of 20-fingers (channel mask length, L = 1μm,finger width, W = 50μm) gate with high resistivity substrate and body-contact. Excellent agreement is achieved between simulated and measured results for DC, S- parameters (10MHz-0.01GHz), and power characteristics, which shows our model is accurate and reliable. MM20 is improved for RF-SOI LDMOS large-signal applications. This model has been implemented in Verilog-A using the ADS circuit simulator (hpeesofsim). 提出了一种新的基于Philips MOS Model20(MM20)的RF-SOI(radio frequency silicon-on-insulator)LDMOS(laterally diffused MOS)大信号等效电路模型.描述了弱雪崩效应以及由热效应引起的功率耗散现象.射频寄生元件由实验测得的S参数解析提取,并通过必要的优化快速准确地获得最终值.模型的有效性是通过一20栅指(每指栅长L=1μm,宽W=50μm)体接触高阻RF-SOI LDMOS在直流,交流小信号和大信号条件下的实验数据验证的.结果表明,直流、S参数(10MHz^20.01GHz)以及功率特性的仿真和实验测得数据能够很好地拟合,说明本文提出的模型具有良好和可靠的精度.本文完成了对MM20在RF-SOI LDMOS大信号应用领域的拓展.模型由Verilog-A描述,使用ADS(hpeesofsim)电路仿真器.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第10期1922-1927,共6页 半导体学报(英文版)
基金 国家自然科学基金资助项目(批准号:60706002)~~
关键词 RF-SOI LDMOS large-signal model MOS Model 20 harmonic power VERILOG-A RF-SOI LDMOS 大信号模型 MOS Model 20 谐波功率 Verilog-A
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  • 1Yang Y ,Yi J ,Kim B. Accurate RF large-signal model of LDMOSFETs including self-heating cffect. IEEE Trans Microw Theory Tech,2001,49(2) :387
  • 2Draxlcr P, Lanfranco S, Kimball D, et al. High efficiency envelope tracking LDMOS power amplifier for W-CDMA. IEEE Microw Symposium Digest,2006:1534
  • 3Moronval X, Peyrot P. Industry first 100W two-stage RFIC for 900MHz GSM EDGE basc station applications. IEEE Microw Symposium. 2007 : 1585
  • 4Costa J, Carroll M, Jorgenson J, et al. A silicon RFCMOS SOI technology for integrated cellular/WEAN RFTX modules. IEEE Microw Symposium, 2007 : 445
  • 5Cassan C, Gola P. A 3.5GHz 25W silicon LDMOS RFIC power amplifier for WiMAX applications. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,2007:87
  • 6Aarts A C T, Swanenberg M I, Kloosterman W J. Modeling of high-voltage SOI-LDMOS transistors including self-heating. Simulation Semicond Processes Devices (SISPAD) ,2001:246
  • 7D'Halleweyn N V T,Benson J,Redman-White W,ct al. MOOSE: a physically based compact DC model of SOI LDMOSFETs for analogue circuit simulation. IEEE Trans Comput-Aided Des Intcgr Circuits Syst,2004,23( 10):1399
  • 8Jang J, Amborg T, Yu Z, et al. Circuit model for power LDMOS including quasi-saturation. Simulation Semicond Processes Devices (SISPAD), 1999 : 15
  • 9Jang J, Tornblad O, Arnborg T, et al. RF LDMOS characterization and its compact modeling. IEEE MTT-S Digest,2001,967
  • 10Aarts A, D' Halleweyn N ,van kangevelde R. A surface-potentialbased high-voltage compact LDMOS transistor model. IEEE Trans Electron Devices, 2005,52 (5) : 999

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