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新型高速低功耗显式脉冲触发器电路设计 被引量:2

Design of Low Power and High Performance Explicit-Pulsed Flip-Flops
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摘要 提出了两种新型脉冲触发器结构——EXPAND触发器和EXPAND-TG触发器.同传统结构相比,新结构一方面通过减小中间节点电容提高电路充放电速度,另一方面通过消除信号竞争避免直流短路电流对电路速度和功耗的影响.同其他文献报道的结构相比,新结构在功耗和速度上均有明显的改进. The speed and delay of flip-flops are critical to the performance of digital circuit systems. Two novel structures for dualedge triggered explicit-pulsed flip-flops are proposed in this paper. The charging and discharging times are greatly reduced due to the lower capacitance of the interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. The flip-flops are also superior to the structures reported in the literature in terms of both power dissipation and working speed.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第10期2064-2068,共5页 半导体学报(英文版)
基金 国家大学生创新性实验计划资助项目~~
关键词 数字电路 触发器 高速 低功耗 脉冲 digital circuits flip-flops high speed low power pulse
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参考文献6

  • 1Tschanz J, Narendra S, Chen Z P, et al. Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flipflops for high-performance microprocessors. International Symposium on Low Power Electronics and Design,2001:147
  • 2Chandrakasan A, Bowhill W J, Fox F. Design of high-performance microprocessor. Piscataway, NJ : IEEE Press, 2001
  • 3Kawaguchi H, Sakurai T. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J Solid-State Circuits, 1998, 33 : 807
  • 4Rabaey J, Chandrakasan A, Nikolic B. Digital integrated circuits : a design perspective. 2nd ed. New Jersey: Prentice Hall,2003
  • 5Zhao P, Darwish T, Bayoumi M. Low power and high speed explicit-pulsed flip-flops. The 45th Midwest Symposium on Circuits and Systems Conf,2002,2 : Ⅱ-477
  • 6Zhao P, Darwish T, Bayoumi M. High-performance and low-power conditional discharge flip-flop. IEEE Trans Very Large Scale Integr Syst,2004,12:477

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