曙光5000高性能计算机Barrier网络的设计

Design of Barrier Network of Dawning 5000 High Performance Computer

为优化Barrier操作的性能,提高大规模并行计算应用在曙光5000系统中的执行效率,文中提出了一种基于硬件的Barrier加速设计.该设计是采用树形Barrier算法,通过增强曙光5000互联网络交换芯片的功能,实现低延迟、可扩展、高可靠和可管理的Barrier网络.该网络支持并发16个Barrier操作,可在Fat-Tree拓扑环境下实现较低的Barrier操作延迟.相比已有实现,是更适合Fat-Tree拓扑的设计方案.理想情况下,1024个节点的同步操作在1.7μs内完成.根据Barrier操作归约和分发过程的特点,分别采用请求应答和超时催促两种机制,为Barrier操作的可靠性提供保障.以该设计实现的Barrier网络原型系统已通过FPGA验证.

To lower barrier operation＇s latency and improve large-scale parallel applications＇ efficiency in Dawning 5000 system, this paper proposes a hardware-based accelerating solution to barrier. The design, which implements tree-based barrier by enhancing Dawning 5000 switch chip, has features of low latency, high sealability, high reliability, and high serviceability. Dawning 5000 barrier network supports 16 concurrent barrier operations. Compared with related works in Fat-tree topology, it is a more proper solution. In ideal situation, the barrier operation of 1024 nodes can be finished within 1.7 microseconds. Based on characteristics of barrier reducing and distributing, two different mechanisms are used to guarantee reliability. The prototype system of proposed design has been verified on FPGA platform.