混合定变长码的测试数据压缩方案

A Test Data Compression Scheme Based on Mixed Fixed and Variable Length Coding

文章提出了一种混合定变长码的测试数据压缩方案,该方案可以有效压缩芯片测试数据量.此压缩方案将代码字拆分为固定长度的首部和可变长度的尾部两部分.首部固定使解压过程简单,硬件开销小;尾部可变使编码灵活.同时采用了将尾部最高位隐藏的方法来进一步提高压缩率,还使用了特殊的计数器来进一步简单化解压电路.对ISCAS89部分标准电路的实验结果显示,文中提出的方案在压缩效率和解压结构方面都明显优于同类压缩方法,如Golomb码、FDR码、VIHC码、v9C码等.

A test data compression scheme based on fixed and variable length coding （FAVLC） is presented, by using which the test data can be compressed efficiently. In the scheme code words is divided into fixed length head, which eases the control of decompression, and variable length tail, which adds the feasibility of encoding. In order to obtain further compression effect, the highest bit of the tail is reduced from the code words. In addition, a special shift counter is also used, which further ease the control circuit. Experimental results show that the proposed scheme obviously outperforms the traditional coding methods in the compression ratio and the implementation of decompression, such as Golomb, FDR, VIHC, v9C coding.