两种新型低时钟摆幅TSPC触发器

Two novel types of low clock-swing TSPC flip-flops

为了降低时钟系统的功耗，提出了2种适合于低功耗应用的基于真单相时钟（TSPC）锁存器的低时钟摆幅触发器：一种是低时钟摆幅边沿触发TSPC触发器（LCSETTFF），另一种是低时钟摆幅脉冲触发TSPC触发器（LCSPTTFF）以及它的几种改进形式。这2种触发器都具有结构简单、功耗低并能降低时钟网络功耗的优点。利用0．18μm CMOS工艺在HSPICE中的仿真表明，与传统的触发器相比，LCSETTFF可以使功耗降低42％，而提出的几种形式的LCSPTTFF可以使功耗和功耗延时积分别降低45％～60％和11％～27％；此外，LCSETTFF和LCSPTTFF的时钟网络功耗可分别降低约56％和78％。实验还表明该文所提出的触发器在嵌入逻辑以提高电路总体性能方面有明显的优势。

Two types of low clock-swing true single phase clock （TSPC） flip-flops suitable for low-power applications were developed to reduce the clock system power consumption, a low clock-swing edge-triggered TSPC flip-flop （LCSETTFF） and a low clock-swing pulse-triggered TSPC flip-flop （LCSPTTFF） developed in several styles. Both types of flip-flops have simple structures, low power, and much lower clock network power dissipation. The circuits were simulated in HSPICE with 0.18 μm CMOS technology. The simulations show that the power of LCSETTFF can be reduced by 42%, while the power dissipation of the LCSPTTFF can be reduced by 45% ～ 60% and the PDP can be reduced by 11% 27%. The power consumption of the clock network with the LCSETTFF can be reduced by 56% and with the LCSPTTFF by 78% compared with conventional flip flops. The advantages of the logic embedding in the flip-flop structures to enhance their overall performance are demonstrated by experiments.