一种带指令高速缓存的8051 IP

Wrapping 8051 core with ICACHE into a standard IP

为设计面向AMBA的SoC集成,将8051兼容内核封装成为带32位AHB总线接口的标准主设备IP,采用了8051内核的高段外部数据空间映射成分页的4 GB SoC空间。设计中采用了嵌入式FLASH器件作为程序存储器,并为提高系统性能而设计了128字节直接映射结构的指令高速缓存。封装成的处理器IP在0.18μm工艺下可工作在200 MHz。利用如Keil uVision等8051兼容工具进行软件开发。测试结果表明,该处理器IP在SoC集成中具有灵活性,借助软、硬件复用,提高了设计效率,具有良好的实用价值。

8051-compatible core was wrapped with 32 bit AHB bus interface into a standard master device IP for the AMBA SoC integration. Higher part of the 8051-core＇s external data space was used to map the d GB SoC space in pages. Embedded FLASH was used as program memory, and a 128 bytes, direct-associated instruction cache was added, aiming at increasing performance. The wrapped processor can run at 200 MHz speed given 0.18 μm process is used. 8051-compatible tools like Keil uVision 1DE can be used to develop software. The wrapped processor IP is flexible for SoC integration and it increases design efficiency by means of design-reuse, from which real implementations can benefit.