摘要
提出了基于准浮栅技术的1.2V全差分运算放大器。由该准浮栅全差分运算放大器实现了一个12位并行结构的电容定标数模转换器(DAC)。所设计的DAC通过按比例缩放方法由两个6位并行DAC组合构成,在提高其分辨率的同时减少了DAC所需的芯片面积,解决了匹配精度随分辨率的增加而下降的问题。最后给出了该DAC的模拟仿真结果。
A 1.2V fully differential operational amplifier (op amp) based on Quasi-Floating Gate (QFG) technique is proposed A 12bit parallel capacitor scaling Digital-Analog Converter (DAC) is realized using the QFG fully differential op amp. The designed DAC is composed of two 6bit DACs by scaling methods. Therefore, as DAC resolution increases, the matching accuracy should not appreciably decrease and the area required for the DAC is also reduced. Finally, its simulation results is also given.
出处
《电路与系统学报》
CSCD
北大核心
2008年第5期44-47,共4页
Journal of Circuits and Systems
基金
国家自然科学基金资助项目(60476046.90207022)
国家部委基金资助项目(51408010304DZ0140)