基于FPGA的高频时钟电路设计

The Design of High Frequency Clock Circuit with FPGA

本文介绍了运用FPGA和时钟芯片,产生高达1G的高频时钟的电路设计方法.经过调试电路达到了设计要求,证明该设计是合理的。

This paper proposes a design method which can generate high frequency up to 1GHz with FPGA and clock-synthesizer.It can achieve our design requirements by debugging,which prove the design is reasonable.