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一种新型7.5GHz 3.4mA相位切换三模预分频器 被引量：2

A 7.5GHz 3.4mA triple-modulus prescaler based on novel phase-switching technique
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摘要 提出了一种新型基于相位选择结构的三模预分频器,与传统结构相比,提供了更多可选的分频比和更宽的输出频率覆盖范围,同时不增加电路复杂度与功耗,可以应用于支持多种无线标准的超高频频率合成器。设计采用了TSMC 0.18μm Analog/RF CMOS工艺,电源电压2.0V。仿真结果表明,电路最高工作频率为7.5GHz,最大电流消耗小于3.4mA。 A triple-modulus prescaler based on novel phase-switching is proposed in this paper. It provides more division ratio and wider frequencies cover range without the additional complexity and power, can be applied to ultra-high frequency synthesizers for different wireless standards. The prescaler is fabricated in TSMC 0.18um Analog/RF CMOS process. The simulation shows it demonstrates a maximum operating frequency of 7.5GHz with less than 3.4mA current in 2V supply voltage.
作者 曲勃 周健军 莫亭亭 李章全
机构地区 上海交通大学微电子学院
出处 《信息技术》 2008年第10期38-40,共3页 Information Technology
关键词 频率合成器 预分频器 相位切换 电流模逻辑 切换窗口 frequency synthesizer prescaler phase-switching CML switching windows
分类号 TN432 [电子电信—微电子学与固体电子学] TN722 [电子电信—电路与系统]
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参考文献4

  • 1Peng Y H, Lu L H. A 16-GHz triple-modulus phase-switching prescaler and its application to a 15-GHz frequency synthesizer in 0.18-μm CMOS[J]. IEEE Transaction on Microwave Theory and Techniques, 2007,51:44-51.
  • 2Craninckx J, Steyaert M S J. A 1.75-GHz/3-V dual-modulus divideby-1.28/129 prescaler in 0.7-μm CMOS[J]. IEEE Journal of Solid- State Circuits, 1996,31:890 - 897.
  • 3Shu Keliu, Sanchez-Sinencio E, Silva-Martinez J, et al. A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier[J]. IEEE Journal Solid-State Circuits, 2003,38:866 - 874.
  • 4Yu XP,Do M A, MaJG, et al.Low power high speed CMOS dualmodulus prescaler design with imbalanced phase switching technique [J]. IEE Proc. Circuits, Devices & Systems, 2006, 152(2):127-132.

同被引文献19

  • 1Wang Shengyang, Zhu Jiafeng, Qu Zhihua. Power efficient multimodulus programmable frequency divider with half-integer division ratio step size[J]. Electronics, Circuits and Systems, 2009, 25 (9) 739-742.
  • 2Hassan H, Anis M, Elmasry M. MOS current mode circuits: analysis, eesign, and variability [J]. IEEE Transactions on Very Large Scale Integration Systems, 2005, 13(8): 885-898.
  • 3Green M, Singh U. Design of CMOS CML circuits for high-speed broadband communications[J]. Circuits and Systems, 2003, 2(2): 204-207.
  • 4Musa O, Shams M. An efficient delay model for MOS current-mode logic automated design and optimization[J]. Circuits and Systems I, 2010, 57(8): 2041-2052.
  • 5Singh U, Green M M. High-frequency CML clock dividers in 0.13μm CMOS operating up to 38 GHz[J]. Solid-State Circuits, 2005, 40(8): 1658-1661.
  • 6Alioto M, Pancioni L, Rocchi S, et al. Modeling and evaluation of positive-feedback source-coupled logic [J]. Circuits and Systems I, 2004, 51(12): 2345- 2355.
  • 7Gu Qun, Xu Zhiwei, Huang Daquan, et al. A low power V-band CMOS frequency divider with wide locking range and accurate quadrature output phases[J]. Solid-state Circuits, 2008, 43(4): 991-998.
  • 8Ng H T, Allstot D J. CMOS current steering logic for low-voltage mixed-signal integrated circuits[J]. IEEE Transactions on Very Large Scale Integration Systems, 1997, 5(3): 301-308.
  • 9Hevdari P. Design and analysis of low-voltage current-mode logic hullers[C] // Proceedings of the Fourth International Symposium on Quality Electronic Design. Washington: IEEE Computer Society, 2003: 293-298.
  • 10Hevdari P, Mohanavlu R. Design of ultrahigh-speed low-voltage CMOS CML buffers and latches [J]. IEEE Transactions on Very Large Scale Integrated Systems, 2004, 12(10): 1081-1093.

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信息技术
2008年 第10期

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