某仿真系统总线接口的设计

Design of Bus Interface in a Certain Simulation System

QBus总线和MⅢ总线为并行数据通讯总线,总线接口用于实现仿真系统中QBus总线和MⅢ总线的数据发送和接收,对QBus总线和MⅢ总线进行监控;介绍了仿真接口的总体设计方案、组成和功能,实现了仿真接口功能的各个模块的硬件设计,并分析了MⅢ总线的数据通讯时序,整个设计过程采用模块化通用设计,最终用FPGA实现了接口板的各项逻辑功能。

The QBus and MⅢ are parallel bus, The bus interface simulates equipment to send data and receive data, and monitors the communication of QBus and MⅢ. Introduce the component and the functions of the interface, design the modules of the function. The detailed description to various hardware modules are presented, and finally the main logical functions of the interface card are realized by FPGA.