多分辨率非整数倍图象缩放的硬件快速算法

Fast Algorithm for Multi-Resolution Non-Integral Image Scaling Based on Hardware

本文针适时对图象处理中,多种分辨率格式的图象变换时,对非整数倍图象缩放的处理,提出了一种硬件快速流水线算法,将双线性插值运算中的除法运算变成乘法运算,将浮点小数运算变成整数定点运算,该算法消除了运算过程中的除法运算,解决了硬件实现快速数学运算的难题。这一算法用于把多种TTL和LVDS数字图像信号变换为适合LCD屏幕的一种信号,通过仿真和在FPGA器件上验证,具有时间短,占用FPGA硬件资源少的特点,效果显著。

In real-time image processing, sometimes it is necessary to use a hardware method for non-integral image scaling, but the difficulty is to realize the hardware mathematic algorithm in high speed. This paper proposes a hardware fast pipelining algorithm for non-integral image scaling. In this algorithm, multiplication operation is used to replace division operation and floating-point operation is converted into pure integer operation. So the operation speed is increased and the used FPGA resource is reduced. The algorithm is easier to be realized with hardware. This algorithm has been used to transform some TTL and LVDS digital image signals into a signal adapting to LCD screen more effectively.