RISC CPU的边界扫描电路设计与实现

Design of boundary-scan circuit in RISC CPU

随着集成电路设计规模不断地扩大、复杂性不断地提高,芯核的可测性已成为设计中不可忽视的环节。边界扫描测试技术作为其中一种方法已被广泛地接受和使用。它能够有效地缩短测试施加时间,提高故障诊断率。本文讨论了边界扫描电路的基本结构和测试思想,设计并实现了RISC CPU中的边界扫描电路,电路结构采用Verilog HDL描述,最后使用Modelsim进行仿真并给出仿真结果。

With the scale and complexity of integrated circuit design expanding, the design for testability for circuit becomes the important part, which can not be ignored. As the one of DFT technologies, boundary-scan has been widely accepted and used. It can reduce test application time, improve fault detection rate. The basic structure and test ideas of Boundary-scan circuit are discussed in the paper. Also, the boundary scan circuit of RISC CPU is designed and implemented with Verilog HDL. Finally, the simulation result of the circuit is provided.