结构化LDPC码的高速编译码器FPGA实现

FPGA Implementation of High-Throughput Irregular Structured LDPC Encoder and Decoder

提出一种高吞吐量、低复杂度、可扩展的非正则低密度校验(Low density parity check,LDPC)码准并行编码结构及译码结构及其实现方案,该编码结构和译码结构针对不同码长的非正则结构化LDPC码可进行相应扩展。通过对编译码算法、优化编译码结构进行调整,降低了编译码器硬件实现中的关键路径迟延,并采用Xilinx公司的Virtex-4 VLX80 FPGA芯片实现了一个码长10 240,码率1/2的非正则结构化LDPC码编码器和译码器。实现结果表明:该编码器信息吞吐量为1.878 Gb/s,该译码器在采用18次迭代情况下信息吞吐量可达223 Mb/s。

Low-density high-speed reconfigurable encoding and decoding architectures, are proposed with the field programmable gate array（FPOA） implementation of irregular structured low density parity check（LDPC） codes. The enhanced semi-parallel encoding and decoding architectures are easily scalable and reconfigurable for different block sizes. Encoding and decoding algorithm transformation and architectural level optimizations are used to reduce the critical path in the FPGA implementation. Based on the architecture, encoder and decoder of irregular structured LDPC codes （10 240, 5 120） are implemented on Xilinx FPGA Virtex-4 VLX80. The FPGA implementation results show that the irregular I.DPC encoder can achieve a maximum（source data） encoding throughput of 1. 878 Gb/s and the irregular decoder can achieve a maximum（source data） decoding throughput of 223 Mb/s at 18 iterations.