雷达视频信号模拟器的硬件设计与实现

Hardware design and implementation of a radar video signal simulator

介绍一种基于TMS320C6713和FPGA的雷达视频信号模拟器,给出一种可实时模拟多批次目标回波的雷达信号模拟器实现方案。重点介绍系统硬件电路的设计,并提出一种自适应单环总线结构,用于数据的快速下载;在视频信号的生成过程中,不同于大多数视频模拟器的杂波数据通过USB或PCI总线将PC机的数据实时传输至硬件电路的缓存单元,而是通过上述总线将杂波、噪声及目标参数等数据事先一次性下载至硬件电路的Flash存储器中。在生成视频信号时,各通道分别从对应的Flash中读取数据,这样,可使系统最大数据吞吐量达到240MB/s,完全满足产生视频信号的实时性要求。

This paper introduces a kind of video signal simulator based on DSP（TMS320C6713） and FPGA.In order to help to design hardware circuit and its realization of the system,a self-adaptive single-ring bus is proposed to download clutter and noise data quickly.In the process of generating the video signal,clutter, noise and objectives parameters are downloaded into Flash memories one-timely instead of downloading clutter data real-time into via USB or PCI bus to cache module on hardware circuit as used in most simulator.Data for each channel are read from corresponding Flash to produce video signal real-timely.In this mode,the maximum data handling capability of the system can reach 240MB/s,which can fully meet the real-time video signal simulation.