期刊文献+

SAGA:一种由流特性制导的微处理器高速缓存分配策略 被引量:1

SAGA: A Stream Attribute Guided Cache Allocation Policy for Microprocessors
下载PDF
导出
摘要 传统的缓存替换策略,如广泛使用的LRU算法,在程序工作集大于缓存容量的情况下,不能有效开发流式数据的重用性,导致缓存性能很差.文中提出一种流特性制导的缓存分配策略(SAGA).该策略利用流检测引擎来发掘程序中的流特性信息,进而动态地在发生缓存缺失时指导是否为缺失数据分配缓存块,最终提高数据缓存的性能.实验表明,对于SPEC2000FP程序集,在1MB缓存上,比较于LRU策略,使用SAGA策略时缓存的缺失平均减少了31%,程序平均CPI降低4%. Traditional cache replacement schemes such as the commonly used LRU policy often fail to exploit reuse of stream data when the working set size of the application is bigger than the cache size,resulting in poor cache performance.In this paper,the data cache performance is improved by enhancing LRU policy with a novel Stream Attribute Guided Cache Allocation(SAGA) policy,which dynamically utilizes streaming information in applications detected by stream engines on microprocessors to guide whether allocate a new cache line or not when a cache miss occurs.Experiments show that SAGA outperforms LRU by 31% in terms of cache misses and 4% in terms of CPI for SPEC2000FP benchmark on a 1MB cache.
出处 《计算机学报》 EI CSCD 北大核心 2008年第11期1929-1937,共9页 Chinese Journal of Computers
基金 国家自然科学基金(60573100 60773149) 国家"八六三"高技术研究发展计划项目基金(2008AA01Z108)资助.
关键词 高速缓存 替换策略 cache replacement policy stream
  • 相关文献

参考文献17

  • 1Lin J, Jaleel A, Chen Y, Li W, Tang Z. Memory characterization of SPEC CPU2006 benchmark suite//Proceedings of the Workshop for Computer Architecture Evaluation of Commerical Workloads (CAECW), Co-Located with HPCA. 2008
  • 2Chen Y, Jaleel A, Li W, LinJ, Tang Z. Memory characterization of emerging recognition-mining-synthesis workloads for multi-core processors//Proceedings of the Workshop for Computer Architecture Evaluation of Commerical Workloads (CAECW), Co-Located with HPCA. 2008
  • 3Jouppi N. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers//Proceedings of the 17th Annual International Symposium on Computer Architecture. Seattle, WA, USA, 1990: 364-373
  • 4Palacharla S, Kessler R. Evaluating stream buffers as a secondary cache replacement//Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, IL, USA, 1994; 24-33
  • 5Mohan T, Supinski B, McKee S, Mueller F, Yoo A, Schulz M. Identifying and exploiting spatial regularity in data memory references//Proceedings of the ACM/IEEE Supercomputing Conference. Washington, DC, USA, 2003:49
  • 6Hughes C, Grzeszczuk R, Sifakis E, Kim D, Kumar S, Selle A, Chhugani J, Holliman M, Chen Y. Physical simulation for animation and visual effects: Parallelization and characterization for chip multiprocessors//Proceedings of the 34th International Conference on Computer Architecture. San Diego, California, USA, 2007:220-231
  • 7Hur I, Lin C. Memory prefetching using adaptive stream detection//Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture. Orlando, Florida, USA, 2006:397 -408
  • 8Nesbit K, Smith J. Data cache prefetching using a global history buffer//Proeeedings of the 10th International Symposium on High Performance Computer Architecture. Madrid, Spain, 2004:96
  • 9Megiddo N, Modha DS. ARC: A self-tuning, low overhead replacement cache//Proceedings of the 2nd USENIX Conference on File and Storage Technologies. San Francisco, CA, USA, 2003:115-130
  • 10Jiang S, Zhang X. LIRS: An efficient low inter-reference recency set replacement policy to improve buffer cache performance//Proceedings of the 2002 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems. Marina Del Rey, CA, USA, 2002: 31-42

同被引文献15

  • 1Denning P. The working set model for program behavior[J].Communications of the ACM,1969,(05):323-333.
  • 2Mattes on R,Gecsei J,Slutz D. Evaluation techniques in storage hierarchies[J].IBM Journal of Research and Development,1970,(02):78-117.
  • 3Qureshi M,Jaleel A,Part Y. Adaptive insertion policies for high performance caching[A].New York:ACM,2007.381-391.
  • 4Keramidas G,Petoumenos P,Kaxiras S. Cache replacement based on reuse-distance prediction[A].Los Alamtios,CA:IEEE Computer Society,2007.245-250.
  • 5Liu W,Yeung D. Enhancing LTP-driven cache mangement using reuse distance information[J].Journal of Instruction-Level Parallelism,2009,(02):1-24.
  • 6Palacharla S,Kessler R. Evaluating stream buffers as a secondary cache replacement[A].Los Alamitos,CA:IEEE Computer Society,1994.24-33.
  • 7Intel. Intel 64 and IA-32 architectures optimization reference manual[R].Santa Clara,USA:Intel,2008.
  • 8Puzak T R. Analysis of cache replacement-algorithms[D].Amherst,USA:Umass,1985.
  • 9Basu A,Kirman N,Kirman M. Scavenger:A new last level cache architecture with global block priority[A].Los Alamitos,CA:IEEE Computer Society,2007.421-432.
  • 10Petoumenos P,Keramidas G,Kaxiras S. Instruction-based reuse-distance prediction for effective cache management[A].Los Alamitos,CA:IEEE Computer Society,2009.49-58.

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部