具有拥塞缓解策略的动态虚拟通道研究及其VLSI实现

Research and VLSI Implementation of a Dynamic Virtual Channel Structure with Congestion Awareness Scheme

虚拟通道技术改善了片上网络性能,却带来了巨大的面积与功耗开销.通过分析静态虚拟通道的不足,提出了基于拥塞缓解策略的动态虚拟通道结构.它采用链表方式组织缓冲,可以自动调整通道结构来适应各种流量负载:在较低流量下,该结构扩展通道队列深度,减小了报文传输延迟;在较高流量下,它增加虚拟通道数量,消除队列头阻塞与通道不足阻塞,并缓解拥塞现象发生,减少流反馈次数,提高了网络吞吐率.在90nm CMOS工艺下完成了DVC路由器的VLSI设计,与传统路由器相比,不仅改善了报文传输延迟与吞吐率,而且有效降低了面积与功耗开销.

The virtual channel flow control approach provides an efficient way for the high throughput of on-chip routers.However,allocating the virtual channels statically results in a waste of area and energy consumption.Through the analysis towards shortcomings of statically-allocated virtual channels,a novel dynamic virtual channel structure with congestion awareness scheme is proposed.The buffer resources are organized by linked lists and their structures regulated according to the traffic conditions.In low traffic,it produces few deep channels to reduce the packet latency.In high traffic,it dispenses many VCs and avoids congestion situations to improve the throughput.The VLSI implementation of DVC router is completed under 90nm CMOS process.The experiment results show that the DVC router which suits for the various inject ratios and traffic patterns can provide throughput increase and latency decrease,with the obvious savings of silicon area and power consumption when compared to traditional routers.