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嵌入式处理器动态分支预测机制研究与设计 被引量:4

Research and Design of Dynamic Branch Prediction Mechanism for Embedded Processor
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摘要 针对嵌入式处理器的特定应用环境,通过对传统神经网络算法的改进,结合定制的分支目标缓冲,提出一种复合式动态分支预测机制。该机制基于全局索引方式,对BTB结构进行定制设计,实现对循环逻辑中最后一条分支指令的精确预测。实验结果表明,该动态分支预测机制能降低硬件复杂度,提高预测精度。 Aiming to the specific application environment of embedded processors, this paper gives a hybrid mechanism which combines custom-designed Branch Target Buffer(BTB) with improved neural network arithmetic for the dynamic branch prediction. In this mechanism, neural network arithmetic implements an approach of global indexing with less resource rather than the normal indexing way based on the instruction address. In use of the unique feature of embedded applications, the BTB structure makes accurate prediction for the final branch instruction in the loop logic. The result indicates that this mechanism achieves high precision with lower complexity.
出处 《计算机工程》 CAS CSCD 北大核心 2008年第21期163-165,共3页 Computer Engineering
关键词 复合分支预测 神经网络 分支目标缓冲 嵌入式处理器 SimpleScalar模拟 hybrid branch prediction neural network Branch Target Buffer(BTB) embedded processor SimpleScalar simulation
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参考文献5

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同被引文献16

  • 1汪永威,樊晓桠,黄小平.32位RISC微处理器中分支预测器的硬件实现[J].计算机应用研究,2009,26(2):419-421. 被引量:3
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  • 3张福新,章隆兵,胡伟武.基于SimpleScalar的龙芯CPU模拟器Sim-Godson[J].计算机学报,2007,30(1):68-73. 被引量:25
  • 4陈智勇.流水线微处理器的设计与实现[J].桂林电子科技大学学报,2007,27(3):219-223. 被引量:4
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