一种高效CAVLC编码结构的VLSI设计实现

Novel high efficiency VLSI implementation of CAVLC in H.264/AVC

CAVLC是H.264/AVC标准新引入的一项重要特性。通过对已有游程编码结构的分析和改进,提出了一种可满足H.264/ AVC实时编码应用的高效CAVLC编码结构。该结构采用优化的数据处理顺序,提高了系统的吞吐率。同时利用算术结构设计代替查找表所需的ROM,降低了设计的硬件成本。在133MHz频率约束下采用0.18um工艺的综合结果表明,所需的逻辑门数为13114,以较少的逻辑资源实现了HD1080@30fps的实时处理.

Context-based Adaptive Variable Length Coding（CAVLC） is a new and important feature of the H.264/AVC.Based on analysis and modification of the conventional run-length coding architecture,a novel high efficiency VLSI architecture for H.264/ AVC CAVLC encoding is presents in this paper.The main concept is to optimize the scan-order and block pipeline to improve throughput of architecture.Moreover,an approach called arithmetic table structure is exploited to replace look-up-table ROM for reducing hardware resource.With the synthesis constrain of 133 MHz,the hardware cost of the proposed design is 13 114 gates based on 0.18 CMOS technology.Simulations show that the proposed design is capable of real-time processing for HD1080 30fps videos under before-mentioned constrain and cost.