8B10B编解码器在PCI Express总线中的实现

Implementation of an 8B10B Encoder and Decoder for PCI-Express

本文在深入研究8B10B编、解码原理的基础上,利用其DWS特性,用Verilog HDL语言实现编、解码算法的描述,并通过了modelsim仿真。在ISE9.1i平台上综合后下载到FPGA上实现具体的硬件电路,同时分析了系统各项性能。在PCI Ex-press总线上,实现了一个性能良好的8B10B编解码系统,它具有很好的可移植性以及一定的实用价值。

According to the characteristic of DWS, a kind of arithmetic of 8B10B encoder and decoder is implemented with the Verilog HDL language after advanced study the principle of 8B10B encoder and decoder. The hardware circuit is achieved in a FPGA after synthesis on ISE9.1i, and the capability of this system is an analyzed. An 8B10B encoder and decoder system with well capa- bility is implemented based on PCI Express Bus which has a good transplant and practicality.