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软件无线电的可重构流处理器体系结构 被引量:1

Reconfigurable Stream Processor Architecture for Software Radio
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摘要 针对软件无线电中存在通用数字信号处理器(DSP)计算能力不足以及专用基带处理器缺乏扩展性的问题,提出了一种新的处理器:面向软件无线电的可重构流处理器及相应的专用指令集。仿真证明,该处理器的可重构设计具备指令集扩展能力,可以对多种无线通信标准甚至是新的通信标准提供支持;面向软件无线电的流体系结构和专用指令集保证了对多种高速无线基带信号的实时处理,运算能力是通用DSP的5~13倍。该处理器为软件无线电中的硬件设计难题提供了一种新的解决途径。 Software radio is hard to be implemented. This is because that existing general purpose digital signal processors (DSP) are not competent for the works with highly computing intensity and baseband processor has poor scalability and flexibility. In order to get over the disadvantages of general purpose DSP and the baseband processor,the article puts forward a novel architecture of reconfigurable stream processor along with application-specific instruction set for software radio. The simulation results of the proposed processor show that the reconfigurable structure provides instruction set extension which can process not only existing wireless communication standards but also new ones with high efficiency. The results also show that the stream oriented structure and the reconfigurable instruction set for software radio ensure processing high-speed baseband signals in real time. Compared with general purpose DSP,the processor gains improvement of computing performance from five to thirteen times. The main goal of the article is to propose an effective way of designing hardware with both high computational performance and enough adaptive ability for software radio.
出处 《航空学报》 EI CAS CSCD 北大核心 2008年第6期1612-1618,共7页 Acta Aeronautica et Astronautica Sinica
基金 国家自然科学基金(60573101)
关键词 计算机系统设计 可重构流处理器 粗粒度可重构 软件无线电 专用指令集 单指令多数据 computer system design reconfigurable stream processor coarse-grain reconfiguration software radio application-specific instruction set single instruction multiple data
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参考文献11

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二级参考文献1

  • 1任恭海,学位论文,1996年

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  • 1车德亮,李剑川,沈绪榜.LS-DSP数字信号处理器总线的低功耗设计[J].国防科技大学学报,2005,27(2):80-86. 被引量:3
  • 2Michael Schulte,John Glossner,Sanjay Jinturkar,Mayan Moudgill,Suman Mamidi,Stamatis Vassiliadis. A Low-Power Multithreaded Processor for Software Defined Radio[J] 2006,The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology(2-3):143~159

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