摘要
一个可以保证系统控制开销很小的控制架构对于实现实时视频压缩系统来说很重要。从提高处理器外设与内核并行性的角度,分析了乒乓缓冲流水线机制系统的问题所在,提出了一种基于双核DSP查询控制的乒乓缓冲机制流水线的视频压缩系统控制架构,并结合ADSP-BF561的特点实现了基于H.264标准的实时编码系统。经测试,此控制架构可以有效减少编码时间、降低系统丢帧率,提高了系统的工作效率,满足了无人机视频压缩系统的实时性和可靠性要求。
A reasonable control framework which brings no additional overhead is very important to implement the real-time video compression system. With the perspective of improving the parallelism of the on-chip peripherals and the core, this paper analyzes the disadvantages of the ping-pong buffers pipeline mechanism at first, and then introduces an improved control framework based on dual-core DSP polling control and ping-pong buffers pipeline to avoid those disadvantages. An H. 264 based video encoder used this control framework was implemented on the platform of ADSP-BF561, and the experimental results show that the framework can meet the real-time capability and reliability requirements of UAV video compression system by reducing the coding time, decreasing the frame loss frequency and improving system work efficiency.
出处
《无线电工程》
2008年第11期22-24,60,共4页
Radio Engineering
基金
863计划资助项目(2006AA701424)
关键词
实时视频压缩系统
控制架构
双核DSP
乒乓缓冲
real-time video compression system
control architecture
dual-core DSP
ping-pong buffers