基于DSP Builder的格型FIR滤波器的设计与实现

Design and realization of the lattice FIR filter using DSP builder

目的研究提高格型FIR滤波器的运算速度、优化硬件资源利用率的方法。方法研究了格型FIR滤波器结构特点,提出了一种改进的格型FIR滤波器结构。并基于FPGA芯片,利用DSPBuilder技术,将MatLab/Simulink设计工具和QuartusⅡ设计工具有效的结合起来,设计了所提出的改进的格型FIR滤波器。结果通过计算机仿真分析,改进后的格型FIR滤波器的最高工作频率和占用的LE等性能指标有了很大提高。结论DSP Builder是进行数字信号处理的一种有效方法。所提出的改进的格型FIR滤波器能够提高格型FIR滤波器的运算速度,降低硬件资源利用率。

Aim To research the new approach to accelerate the operation and optimize the availability of hardware resource in lattice FIR filter.Methods The structure features of lattice FIR filter were introduced.A new improved structure is presented,and designed by use of DSP Builder Tool which combines MatLab/Simulink and Quartus Ⅱdesign tools in FPGA chips.Results By computer simulating,Max frequency of lattice FIR filter is higher than before,the number of LE used is reduced.Conclusion It is more effective to process digit signal by using DSP Builder.This new improved lattice FIR filter can accelerate the operation and optimize the availability of hardware resource.