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AVS视频图像缩放模块的设计与实现

Design and Implementation of AVS-video Image-scaling Module
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摘要 介绍了应用于AVS视频解码芯片的图像缩放(Scaling)模块。该模块依次通过垂直方向、水平方向进行图像像素重采样,再运用移位和加法运算达到了图像缩放效果。算法是硬件可实现的,图像缩放效果好,视觉感尚佳,硬件成本低。此方案已成功运用到AVS视频解码芯片项目中,实现了图像缩放的功能。 The paper introduces the image-scaling module and its implementation for AVS-video decoded chip. The module resamples the pixel through the vertical and the level direction in correct order, and apply to the shift and the addition to achieve the image-scaling. The algorithm is implemented, and can achieve fine image quality with lower hardware cost. This scheme has already been used in the AVS-video decoded chip project to realize the image-scaling function.
出处 《计算机与现代化》 2008年第11期91-94,共4页 Computer and Modernization
基金 国家火炬计划资助项目(2007GH010120)
关键词 AVS视频解码芯片 视频后处理 图像缩放 图像分辨率 AVS-video decoded chip video post process image-scaling image resolution
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参考文献11

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二级参考文献5

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共引文献8

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