层次化时钟网络设计研究

Hierarchical Clock Trees Design Analysis

层次化设计是复杂芯片开发所采用的主流方法,它是一种自底向上的流程.但层次化设计也带来了时钟树设计难以掌握的问题.文中针对一款复杂SoC系统芯片时钟树设计,详细分析了层次化时钟树综合需要解决的关键难点,并提出了有效的解决方案.实验结果表明,该设计方案可以迅速达到时钟树收敛,提高设计效率.

Hierarchical design, a bottom-up flow that is the main method used in complex IC. Also clock trees synthesis faces some untraceable difficulties along with hierarchical design. The paper analyzes some key points aimed at hierarchical clock trees synthesis in a complicated SaC. Practise indieats that convergence hierarchical clock trees can be achieved rapidly by the solution researched in this paper, also the efficiency.