AFDX网络中基于虚拟计时的警管算法

Virtual-timing-based policing algorithm in AFDX network

要在具体的器件(如FPGA)上实现警管算法,不仅要考虑到算法的正确性和高效性,还要注意可实现性。详细介绍了一种用在AFDX网络的高效、低逻辑资源占用的基于虚拟计时的警管算法,分析了资源占用情况及需要关注的几个问题。该算法已经在Altera公司的FPGA上实现,而且可以推广到其他网络。

To implement policing algorithm in specific device （e. g. FPGA）, designers should not only consider the correctness and efficiency of the algorithm, but also take account of the feasibility. A virtual-time-based policing algorithm used in Avionics Full Duplex Switched Ethernet （AFDX） network, of high efficiency and low logic resources consumption, was introduced in detail. The consumption of resource and several important problems were danalyzed. This algorithm had been implemented in ALTERA＇s FPGA, and could be applied to other networks.