基于FPGA的高分辨率时间数位转换器设计

A Design for FPGA-based Time-to-Digital Converter with High Resolution

介绍时问间隔的测量原理,分析各种测量方法的优缺点和主要误差来源,并设计了一种基于现场可编程门阵列(FPGA)的时数转换器(TDC)。该设计采用高精度计数器和延迟线内插法共同测量时间间隔。该时数转换器的测量范围由计数器决定,而测量分辨率由内插延迟线决定,因此,具有测量范围大,分辨率高的特点。由于测量的利用两种延时单元的微小时间差对时间间隔进行内插,获得了lns的测量分辨率,具有精度高、功耗小及实现简便等优点。

Abstract This paper describes the principle of time interval measuring, analyzes the advantages and disad- vantages of various measuring methods, and the resources where of main errors. A Time - to was designed based on the FPGA. The design combined an accurate digital counter and a delay circuit to make the time interval measurement. The dynamic range of the TDC is determined by Digital Converter line interpolation Digital Counter,and the resolution is determined by delay line interpolation. Therefore, the TDC has the characteristic that the dynamic range is large and the resolution is high. Because taking use of the delay between two kinds logic cells inside the FPGA , the design acquires 1 ns measuring resolution. The system has the following merits： high precision, low power consumption and simple realization.